# quartus_sh -t 
load_package flow
project_new "b7_ftb_1" -overwrite
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CEFA7U19C7
set_global_assignment -name TOP_LEVEL_ENTITY b7_ftb_1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:48:50  JUNE 30, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
set_global_assignment -name VERILOG_FILE ./202307100947.v
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ./output_files
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name EDA_SIMULATION_TOOL VCS
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VERILOG_MACRO "FPGA="
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# execute_module -tool map
set_location_assignment PIN_U13 -to clk
set_location_assignment PIN_AA8 -to rstn
set_location_assignment PIN_AB10 -to sdin
set_location_assignment PIN_AB7 -to sdout
set_location_assignment PIN_Y17 -to lrclk
set_location_assignment PIN_AB18 -to fclk
set_location_assignment PIN_AA15 -to mclk
set_location_assignment PIN_AB21 -to bclk
set_location_assignment PIN_Y9 -to button1
set_location_assignment PIN_AA18 -to button2
set_location_assignment PIN_Y10 -to button3
set_location_assignment PIN_AB13 -to cst[2]
set_location_assignment PIN_AB11 -to cst[1]
set_location_assignment PIN_AA7 -to cst[0]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
# create_clock -name clk -period 20.0 [get_ports clk]
execute_flow -compile
export_assignments
#project_save
project_close

# convert sof to jic: quartus_cpf -c 202307071040.cof


	EPCS256
	5CEFA7U19C7
	output_files/b7_ftb_1.jic
	1
	1
	7
	
		Page_0
		1
		
			output_files/b7_ftb_1.sof
		
	
	5
	0
	
	


quartus_pgm -c 1 -m jtag -o "P;output_files/b7_ftb_1.jic@1"